We will build a BCD-to-decimal 7-segment circuit. The input will be the BCD code of a decimal digit, i.e. a 4-bit input. The
output will be a decimal value displayed in a 7-segment display, with 7 outputs for the 7 segments a~g.
Step 0
You should have completed the Unit 2 Digital Logic Project.
Step 1
Start from the design step.
a. Read ch8.2 Seven-Segment Displays of the Tarnoff textbook.
b. Instead of a circuit to display hexadecimal digits (0~9 and A~F), we will build a circuit to display decimal digits 0~9 only.
c. Truth table: we will only use the first 10 rows of Fig 8-14 from ch8.2. The last 6 rows (for hex A-F) become don’t care
conditions. Include a copy of the revised truth table in your project document. The truth table should still show 16 rows but with
don’t care conditions.
d. Provide a simplified Boolean expression for each of the 7 outputs a ~ g. Use whatever simplification method you like, but
you must use the don’t care cells and show your work with steps (such as k-maps). Creating k-maps on the computer is a
good idea. Make sure another person (not you, as you did the work) can read your groupings and follow how each group is
simplified.
Step 2
Create a circuit in Logisim piece by piece based on your simplification result from Step 1. Only use AND, OR, and NOT gates.
Your circuit should have four inputs and 7 outputs.
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Description
Label every input/output pin and every AND/OR gate in your circuit. Labels are like comments in a program and can help us
track our work, especially when we need to correct errors. Label an AND gate with the term generated, like A’BD’, and an OR
gate with the function name, like W.
Add your name, Park ID, and date to your circuit using the text tool. Save your circuit as Unit3_YourLastName.circ. Test
your circuit to make sure it works properly before proceeding to the next step. Document your testing in the project document.
Step 3
Now attach a 7-segment display to your a~g outputs. Figure 1 shows where a 7-segment display is listed in Logisim. Figure 2
shows the mappings between a~g segments (and the dot) and the 8 pins of the 7-segment display component. The rightmost
pin in the bottom (the dot) is connected to a constant 0 as we don’t need this dot. Use a Constant component (Figure 3) and
change its value attribute to 0. If needed, see the Help menu > Library reference > Input/Output Library > 7-segment Display.
Display
Figure 1
Figure 2
Top four pins from left to right: g f a b;
Bottom three pins from left to right: e d c
Figure 3
Do not delete the a~g output pins when attaching the 7-segment display. Add additional wire before each output component as
shown below. Save your circuit as Unit3_YourLastName_7seg.circ. Test your circuit and document your testing in the
project document.
8/28/24, 3:09 PM Unit 3: Digital Logic Project
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Step 4
Project feedback:
a. What’s the hardest part of this project for you? Please explain.
b. How’s your understanding of simplification and combinational circuits after this project? Please explain. Feel free to
comment on other aspects of this project.
Notes
In Logisim, the wires of a properly connected circuit should only be light green (1) or dark green (0). See Help > User’s Guide
> Wire bundles > Wire colors.
Use one AND gate for each ANDed term no matter how many variables the term uses. Use one OR gate to OR terms at the
same level. Edit the number of input pins an AND/OR gate has to match the number of inputs the gate needs. It can help you
track your work, not missing any input connections or adding extra ones.
Build and test your circuit incrementally for segments a~g. Complete and test the portion for output a (Project menu > Analyze
Circuit) before adding gates and wires for segment b, and so on. You may even save a copy of your work after each segment
is tested (Unit3_a.circ, Unit3_b.circ, …) in case you need to roll back to an earlier working version.
Submit three files: two circuit files and one project document (a Word/Excel/PDF file that includes all other required items). See
the rubric for the required items.
8/28/24, 3:09 PM Unit 3: Digital Logic Project
Submission
